Recent technological trends support decreasing the physical dimensions and applied voltage of storage devices, which may increase the probability of errors in such devices, such as cache arrays or memory devices. A need exists for efficient error correction mechanisms for such devices.
Various methods and systems to integrate error correction mechanisms into processor caches such as L1 caches are known. Error correction (EC) bit generation, and error correction and detection mechanisms often overlap with main processor pipelines. For example, data storage and error correction update may occur in a single pipeline that is expensive and inefficient. Many current EC integration schemes involve a read-modify-write (RMW) mechanism. EC integration schemes that involve a RMW mechanism may stall or interrupt writing a set of data from the cache unit if there is a substantially concurrently read request for the data before the data is fully written. Such schemes may add extra time or computational cycles to execute a write operation. The L1 cache array is highly sensitive to timing and extra computational cycles may degrade performance. A need exists for integrating an efficient error detection and/or correction mechanism into cache units.